Freestanding multilayer IC wiring structure

ABSTRACT

A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit using substantially the same steps. The MEMS structure of this embodiment includes freestanding electrodes which are not fixed to the substrate.

RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No.09/064,546 filed on Apr. 22, 1998, and now issued as U.S. Pat. No.______.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to microelectronics and, moreparticularly, to microelectronics having air dielectric wiring forreduced capacitance or having a cavity which contains micro-mechanicalor micro-electromechanical structures.

2. Background Description

Integrated circuit (IC) performance is dependent upon individual circuitperformance. Individual circuit performance is dependent on the load thecircuit must drive. For field effect transistor (FET) circuits, theprimary load is capacitive. The primary source of the circuit loadcapacitance is inter-circuit wiring capacitance. Thus, IC performancecan be improved by reducing wiring capacitance.

Typical IC chips with a large number of logic circuits include multiplelayers of wires, called wiring layers, stacked one on top of another andseparated by dielectric material. The ideal dielectric is air or, atleast has the same dielectric constant as air. There are severalapproaches to providing an air dielectric in IC chips.

Another type of microelectronic chip includes micro-electromechanical(MEM) devices, preferably integrated on the same substrate withtransistors and their interconnections. Motion of the MEM devicesrequires that they be within a gas or vacuum filled cavity.

Freestanding Wiring Structures

One approach is to remove the dielectric around the wires, suspendingthe wiring in air. The suspended wires are uncovered with any dielectricand are supported, mechanically, only by interlevel metal studs used toform the circuit. Although scanning electron microscopic (SEM) images ofsuch structures clearly show that small lengths of wire are selfsupporting, longer lengths of wire are not self-supporting. So, longerlengths of unsupported wire are susceptible to shorting.

For example, U.S. Pat. No. 4,899,439 entitled “Method of Fabricating AHigh Density Electrical Interconnect” to Potter et al. teaches buildingpillars from the substrate under the wires extending upward to upperwiring levels wherever support is required. However, because wiringchannels must be allocated for these pillars, the pitch or density ofwires is reduced by as much as half.

Another approach is to stiffen the wires, such as taught in U.S. Pat.No. 5,148,260 entitled “Semiconductor Device Having an Improved AirBridge Lead Structure” to Inoue et al., wherein the metal lines areformed from a stiffer composite metal that is less likely to deform thantypical wiring metals. This approach reduces, but does not eliminateshorting in an air dielectric IC structure. Further, Inoue et al., alsorequires including some support pillars, although not as many arerequired as in Potter et al.

Both Potter et al. and Inoue et al. teach structures that are formedusing conventional techniques, with the removable dielectric materialremoved through several repeating layers of metal studs and metal lines.Material may be backfilled around the freestanding wires to provide adielectric other than air.

Gravity is the primary focus in abating shorting problems in prior artfreestanding IC wiring structures. Other accelerations such asvibrations and impact are also a problem. Thus, to counteract gravity, astrong support is provided from below the wires.

The above examples of the prior art incur a substantial wiring densitypenalty because the support pillars extend through several wiringlevels, all the way up from an underlying substrate. These smalldiameter support pillars are formed level by level and so, must be linedup at each level with an underlying level.

To simplify this critical alignment requirement, a stiff intermediateplanar layer may be formed on each support pillar level. Thus, thepillars would support the planar layer and the planar layer supportsanother pillar level. For this type structure, pillars need not line upfrom level to level. However, any dielectric must be removed after theplanar layer is formed by complex venting and filling steps or thedielectric is trapped under the permanent planar layer.

A typical prior art approach, when using planar layers to constructfreestanding structures, is to form an air dielectric on a layer bylayer basis. For example, in U.S. Pat. No. 5,144,411 entitled “Methodand Structure for Providing Improved Insulation in VLSI and ULSICircuits”, to Kaanta et al. (hereinafter Kaanta), a planar dielectriclayer is formed directly below the next higher level of metal lines butabove a lower layer of metal lines or on pedestals above the lower layerof metal lines with a complex process requiring extra masks. Kaantateaches etching access openings through the planar layer, removing thedielectric and plugging the openings. Presumably, the next level ofmetal lines is formed on top of the planar dielectric by Reactive IonEtch (RIE) of a metal layer which was deposited on the planerdielectric. Each successive metal layer is formed on top of a permanentplanar layer of dielectric.

In Kaanta, the wire is anchored on only a single surface of the wire,and that surface is a flat surface on the underside of the wire. Theflat surface, in turn, is anchored to the planar layer. Such astructure, stemming from the RIE method used to pattern the metal on topof the planar layer is susceptible to detachment from shear forces in adirection parallel to the planar layer. A more stable structure isneeded to increase the stability of the structure. Furthermore, it isdifficult to pattern certain metals such as copper by RIE, and thus analternative method is needed.

U.S. Pat. No. 5,444,015 entitled “Larce (sic) Scale IC PersonalizationMethod Employing Air Dielectric Structure for Extended Conductors” toAitken et al. (Hereinafter Aitken), assigned to the assignee of thepresent invention, teaches an approach similar to Kaanta that reducesthe extra masks by forming openings in a removable dielectric for studsand supports simultaneously.

In Aiken, however, the wire is anchored on only a single surface of thewire, and that surface is a flat surface on the underside of the wirewhich is anchored to the planar layer. Such a structure, stemming fromthe deposition of metal onto a completely planar layer, may besusceptible to detachment from shear forces in a direction parallel tothe planar layer.

Also, the support dimensions in Aitken are not as large as studs. Afterforming support openings, Aitken teaches depositing dielectric to fillthe support locations and line stud openings. An anisotropic etchremoves support dielectric from the bottom of the stud openings that arefilled with metal in subsequent steps. Aitken stud opening diametersmust be wider (twice the thickness of the dielectric tube) than thestuds themselves, which must be larger than the minimum processdimension.

Prior art structures are typically supported by pedestals. The circuitdesign tools must keep track of whether inter-level features are studsor pedestals. Further, circuit design is more complicated because thewiring and the support pedestals must be accounted for on each wiringlevel.

None of the methods of the previously discussed prior art is useful whenthe metal lines are patterned by polishing, such as bychemical-mechanical polishing (CMP). The industry is moving towardcopper wiring which is patterned by CMP. A method for forming an airdielectric is needed which is compatible with copper processing.

Although Kaanta and Aitken can both have planar layers in theirstructures, they both suffer from previously mentioned structuralweaknesses toward shear forces.

Freestanding Micro-Electromechanical Structures (MEMS)

Prior art MEM devices use freestanding self supporting structurescomposed of a sequence of polysilicon, metal, or sometimes siliconnitride studs and lines. Structures are supported by the underlyingsubstrate. The interlevel freestanding structure is generally aconductor which is supported by the underlying substrate. In thesestructures, the electrical interconnects are at the substrate level, andthe interconnects can not be made directly to overlying wiring or to theoutside of the structure without first connecting down to the substrate.It is further noted that in the prior art systems, no unrelatedstructures, transistors or wiring are based below the MEM device becausethe substrate is needed for electrical contacts and to support the MEMstructure. See for example, U.S. Pat. No. 5,367,136 to Buck, U.S. Pat.No. 5,578,976 to Yao, Gretillat et. al. in “IEEEMicro-Electro-Mechanical Systems Workshop, 1995, pg. 97-101”, orGoldsmith et. al. in “IEEE Microwave and Guided Wave Letters, 8 No. 8,pp. 269-271.

Although MEMS have been integrated with electrical transistors andcircuits on silicon (Bustillo et. al. Proceedings of the IEEE 85, No. 8,August 1998, on page 1556-1558) there is no known prior art related tointegration of MEMS with electrical transistors and circuits whichinclude wiring surrounded by a gap or air dielectric. There is also noknown structure relating to a combination of MEMS with copper wiring,and more particularly to a combination with copper wiring which alsoincludes an air dielectric.

Generally, MEMS structures are defined in a complete process block,independent of the process blocks used to define the transistors andwiring of the electrical circuits. Since the MEMS also occupy their ownregions of silicon, cost savings are minimal compared to an approachwhich is able to combine a large number of process steps, each of whichcontributes to simultaneous formation of an element of both the circuitand the MEMS structures, or compared to an approach which is able toform MEMS structures above regions of silicon substrate which havetransistors. Bustillo shows a structure (FIG. 5 of reference) where someprocess steps for MEMS formation are interleaved with steps used forcircuit formation; however, the overlap is minimal and circuits can notreside under the MEMS. Bustillo does briefly discuss (but does not showany supporting Figures) a different structure where the independent MEMSprocess block, after completion of the circuitry process block, could bemodified so that circuitry could reside under the MEMS.

Since the MEMS structure is already at the top of the substrate, thereis an advantage that the electrical connections do not need to go backup to overlying wiring. However, there are severe restrictions placedupon the composition and conductivity of the wiring based partly on thefact that the MEMS structure is made of polysilicon and thereforerequires temperatures higher than can be tolerated by many wiringmaterials. A low temperature process by Nguyen could replace thepolysilicon with nickel, but the process would still require a block ofprocesses independent from those required for the CMOS wiring. In anycase, no prior art teaches MEMs overlying transistors with highconductivity wiring or in particular with a high performance dielectric.

Attempts to integrate MEMS with CMOS also pose problems. For instance,polysilicon gates in CMOS do not need to connect to the substrate, butprior art MEMS polysilicon does need to be supported by the substrate.Also, there is a need for BEOL MEMS which can be easily integrated withconventional CMOS BEOL. In particular, it is necessary to be able topattern dissimilar metals on the same level so that the identity of theCMOS metal can be optimized for CMOS and the identity of the MEMS metalcan be optimized for MEMS.

Also, MEMS structures are plagued by stress induced deformation ofelectrodes because electrodes/structures form internal stresses andstrains during the construction of the structure which are relieved bydeformation when the material surrounding the structure is etched toform a “released” or free-standing structure. (See for example Bustillo,page 1559 at the top of the second column.) Very narrow gaps are oftenrequired between the released structure and the counter-electrode on thesubstrate in order for the voltages required to operate the MEM deviceto be low enough so that they are compatible with the voltages requiredin associated electrical circuits. There is thus a trade off betweenwider gaps with higher device yields and a desire for low voltageoperation with corresponding narrow gaps and therefore reduced yields.

Another limitation is that most MEMS structures use one element(electrode) which is freestanding and another element (substrate) whichis not freestanding in fact, the substrate is fixed. Also, a light,stiff moveable element has less susceptibility to acceleration, butdrive voltages are increased (Proceedings of Aerospace conferences,1997, IEEE, p. 285, modulus discussion). There is thus a need tosimultaneously improve both the susceptibility and increased voltages toaccelerations.

Materials and Processing

Materials used in prior art methods for creating air dielectrics areexotic and, so, are expensive to develop and difficult to remove.Kaanta, for example, teaches using parylene as a removable dielectric.Parylene has a low decomposition temperature, which severely restrictsthe materials that can be used for the freestanding structures.

Furthermore, typical prior art methods use aqueous chemicals to etch theremovable material. It is uncertain whether these aqueous chemicals canpenetrate the convoluted paths to regions buried deep within the wiringthat must be cleared of removable dielectric. In particular, whendielectric removal is deferred until the end, or, for structures withvented planar layers such as U.S. Pat. No. 5,324,683 to Fitch et al.entitled “Method of Forming a Semiconductor Structure having an AirRegion” (which is even more complex than Kaanta), these aqueouschemicals penetrate vent holes with considerable difficulty.

Further, after reaction and drying, the reaction products may not beremoved completely from the nearly enclosed air dielectric compartments.These small openings make it difficult for reactants to diffuse in, orfor waste products to diffuse out, when the cavities are filled with aliquid.

Additional problems arise when aqueous HF is used to remove oxides fromthe exposed metal lines. The HF in the aqueous solution can attack themetal, especially when the lines are a composite metal. Electrochemicalpotentials further contribute to corrosion of one metal of thecomposite. Such an attack can result in open electrical circuits, higherline resistivity, and the metal lines separating from their supports.

Thus, there is a need for a way to remove dielectric from metal lineswithout attacking the metal, with adequate penetration of small openingsand subsequent removal of reaction waste products from the structure.Further there is a need for a way to form air dielectric structures onintegrated circuit chips without increasing the number of masks,requiring complex vent and fill procedures or difficult supportalignment.

SUMMARY OF THE INVENTION

It is a purpose of the invention to provide a manufacturable integratedcircuit structure with an air dielectric wiring.

It is another purpose of the present invention to anchor the wiring inan air dielectric structure for mechanical strength to minimize shortsbetween wires.

It is yet another purpose of the present invention to provide amanufacturing process for fabricating integrated circuit structures withair dielectric wiring.

It is yet another purpose of the present invention to simplifymanufacturing integrated circuit structures with air dielectric wiring.

It is yet another purpose of the present invention to provide a methodof manufacturing air dielectric structures that can define wiringsupport after wiring definition.

It is yet another purpose of the present invention to provide a methodof manufacturing air dielectric structures that does not requireremoving the dielectric and forming wires on a weak substrate.

It is yet another purpose of the present invention to provide a methodof manufacturing air dielectric structures using existing integratedcircuits and materials to create the air dielectric structure.

It is yet another purpose of the present invention to provide wiringwhich has a non-planar contact with a planar supporting plane.

It is yet another purpose of the present invention to provide airformation with Copper.

It is yet another purpose of the present invention to providesimultaneous MEMS cavity and air dielectric planar support in wiring andsidewall support in MEMS.

It is yet another purpose of the present invention to provide a processsequence using multiple common steps to lower the costs ofmanufacturing.

It is yet another purpose of the present invention to provide copperwiring with a dissimilar MEMS material between MEMS and wiring.

It is yet another purpose of the present invention to provide an AC/DCswitch and voltage operated capacitor.

It is yet another purpose of the present invention to provide MEMShaving a structure with less sensitivity to stresses and lesssusceptible to acceleration.

It is yet another purpose of the present invention to provide MEMS withhigh electrical conductivity.

It is yet another purpose of the present invention to provide MEMSelements with compliant support.

It is yet another purpose of the present invention to provide MEMSdevices with improved drive voltage/gap trade-off.

It is yet another purpose of the present invention to provide suspensionof MEMS devices without substrate contact which provides a simplifiedconstruction.

It is yet another purpose of the present invention to provide MEMSdevices with unrelated wiring underneath the substrate.

It is yet another purposes of the present invention to improve aneffective dielectric constant and the structure of the class of wiringstructures which include a combination of wires, dielectric supports andair gaps.

The present invention is an air dielectric wiring structure and methodof manufacture therefor. Successively formed wiring layerssynergistically combine with interwire supports, either a subsequentlyformed sidewall or an improved planar layer, to form a self supportingair dielectric interconnection matrix.

Complex venting and plugging problems are avoided by using an easilyremovable dielectric, that can be virtually completely removed. Wiresare supported by vertical sidewalls or an improved planar support layerin combination with wiring studs. An optional dielectric cladding may beleft on the metal wires for short and oxidation protection. Becausesidewalls or planar layers are formed after wiring, with the wiring ateach level providing support definition, complex support alignment isunnecessary.

In one embodiment, sidewalls are formed after removing dielectricbetween the wires support and the otherwise free-standing wires. Thesidewalls hold the wires vertically and connection between thesuccessive perpendicularly aligned wiring levels interact to anchor eachother. The dielectric wiring structure may include a thin dielectriccovering, preferably of the same material as the sidewalls, thatcompletely or partially covers the wiring and extends from each wireside down to lower levels of the air dielectric structure. Thedielectric covering coats and protects the wires and anchors the wiresin position. Thus, the incidence of shorting between wires in the airdielectric structure is reduced.

In the methods of manufacturing the air dielectric structure, aftercompleting wiring layers for an integrated circuit, dielectric,preferably SiO₂ and possibly including nitride planar layers, isisotropically etched away in a pre-defined region, or anisotropicallyetched to a depth traversing at least a part of two or more wiringlayers, leaving each wire on each exposed or partially exposed layer onor embedded within lengthwise SiO₂ pillars. A conformal layer of etchresistant (to SiO₂ etch) material is formed on the etched structure toform sidewalls at each SiO₂ pillar, ie., at the edges of each exposed orpartially exposed wire. Alternately, the previously removed (by theetch) SiO₂ may be replaced with etch-resistant material filling betweenthe wires. The remaining SiO₂ fill is removed through vents formed inthe etch-resistant material.

In another embodiment, fill dielectric is anisotropically sub-etchedaway from the wiring layers by a first etch step, using the circuitwiring as an etch mask. The sub-etch traverses a portion of at least twoorthogonally aligned wiring layers and terminates slightly beforereaching an underlying etch resistant insulating material layer or atthe layer, if the resistant insulating material layer is non-planar. Aconformal layer of an etch resistant insulating material is applied. Thestructure is etched with an anisotropic etch to remove horizontalsurfaces of the conformal coating and, especially to open the conformallayer at the bottom of the structure, thereby exposing the underlyingfill dielectric. The exposed fill dielectric and all fill dielectric incontact with the exposed fill dielectric is then removed.

In one embodiment, the fill dielectric is silicon dioxide and the etchresistant insulating material is silicon nitride. The exposed silicondioxide is etched using reactive ion etching (RIE) to a point above asilicon nitride layer. A thin layer of silicon nitride is thenconformally deposited on the structure. A second anisotropic reactiveion etching step opens the silicon nitride and exposes the underlyingsilicon dioxide. A vapor HF etch is used to remove the remaining silicondioxide until only the silicon nitride, the circuit wiring, or otheretch resistant materials remain and are exposed to air. The result is anembodiment integrated circuit with air dielectric wiring having a thinsilicon nitride layer stabilizing and holding the suspended wires intheir original position.

In another embodiment, a permanent vented planar layer of dielectric isformed on the top of (overlying) each successive wiring layer. The topsurface of the wires of each wiring level is made non-planar, prior todeposition of each permanent vented planar layer. Making the top surfaceof each wire non-planar offers the key advantage that the wiring,especially in long wiring runs to be more resistant to shear stressesthan in prior art structures which include a planar layer whichunderlies the wiring and where the surface of the wire in contact withthe planar layer is also planar. In an embodiment which has even greaterresistance to shear stress, the sides of the wiring layers are taperedand/or the removable material which lies between the wires is furtherrecessed below the top surface of the wiring prior to deposition of thevented planar layer. The removable material is removed through the ventsafter all of the wiring levels are formed. In fact, the vents can beformed after the completion of the wiring levels. An additionaladvantage of the invention is the placement of a planar layer over thetop of the wiring rather than under the wiring. In this manner, thepresent invention is compatible with copper wiring formed by the “dualdamascene” method where lines and studs are simultaneously formed andthe wiring is patterned by Chemical Mechanical Polishing (CMP) afterfilling a trench in a dielectric with copper. The process of the presentinvention requires only a few additional steps to implement with copperwiring.

In another aspect of the invention, the air dielectric wiring iscombined with micro-electromechanical (MEMS) devices. This aspectbenefits from a hybrid of two embodiments described above. Sidewallsupport of the MEMS devices enables use of symmetrical parallelelectrode structures where there is less susceptibility to residualstresses than previously obtainable. The hybrid design also enableseasy, economical combination with copper wiring with an air dielectric.However, the resistance to stress in the sidewall supported MEMS isobtained whether or not the wiring elsewhere on the integrated circuithas an air dielectric. Accordingly, in yet another advantage of thepresent invention only minimal extra steps are required to form thehybrid MEM device.

When the present invention omits wiring down to the substrate whencreating MEMS there is process and structure simplification. Thisfacilitates construction of parallel freestanding structures which givesrise to an additional benefit, i.e., less susceptibility to interferencefrom shock/acceleration, because both parallel structures arefreestanding. For example, when one electrode (substrate) is fixed, thenthe substrate electrode and the freestanding electrode have differingresponse to forces which are felt by both the substrate and theelectrode. Likewise, if the construction shapes are vastly different,then the responses will also be vastly different. If instead of oneelectrode being fixed to the substrate, both the electrodes can move andare symmetric, then there is addition benefit of reduced voltagesrequired for a given deflection. Movement of both electrodes contributeto a change in relative position in contrast to when one electrode isfixed by the substrate. Then, relative motion must come from the singlemoveable electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIG. 1 is a cross-sectional view of wiring, which is preferably in anintegrated circuit with three (3) wiring layers;

FIG. 2 shows the structure of FIG. 1 etched, with the wiring layersserving as masking layers to remove fill oxide from between wires and,thereunder, from fill layers;

FIG. 3 shows a conformal layer of etch resistant material is formed onthe structure of FIG. 2;

FIG. 4 shows horizontal portions of conformal layer removed to leavesidewalls;

FIG. 5 shows an alternate embodiment wherein to minimize exposing thewiring layers to oxide RIE, the sidewall layer is formed stage by stageas each wiring layer is formed;

FIG. 6 shows another alternate embodiment wherein dummy sidewallsprovide extra structural support and the conformal layer may be ventedat a top surface using CMP;

FIG. 7 shows after anisotropically etching the alternate embodiment ofFIG. 6 wherein a resist pattern is transferred to the fill dielectricwhich is further patterned by wiring layers;

FIG. 8A is a top view of the wiring and the sidewall formed at the topwiring layer of FIG. 7;

FIG. 8B is a top view of the wiring and the sidewall formed at bottomwiring layer of FIG. 7;

FIG. 9 shows a variation on the alternate embodiment in FIG. 7, whereinthe surface is masked by resist and supports are formed only in smallunmasked regions;

FIG. 10 shows a top view of another alternate embodiment wherein,instead of using an anisotropic etch, an isotropic etch is used to formthe wiring supports;

FIG. 11 is a cross-section of the embodiment of FIG. 10 at A-A;

FIG. 11 a shows an array of vent holes depicted in FIG. 11 along line 11a-11 a;

FIG. 11 b shows the array of vent holes having overlapping etch fronts;

FIGS. 11 c and 11 d show wiring supported by permanent and removabledielectrics such that the permanent dielectric is removed in portionswhere the removable dielectric is removed;

FIGS. 12 a-12 d shows a structure and method of forming an alternativeembodiment of the present invention having a convex surface over thewiring layer;

FIG. 13 a shows a layered structure of the present invention;

FIG. 13 b shows the formation of vents in the structure of FIG. 13 a;and

FIGS. 14 a-18 c show the several steps of forming a transistorcircuit/MEMS device of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

The inventor of the present invention discovered that gaseous HF may beused to remove silicon dioxide (SiO₂) from a layered wiring structurewithout the normal damage to the wires. The damage that occurred inprior art methods was the result of using an aqueous solution to removefill dielectric. The prior art aqueous solution invariably attacked themetal wires as it removed the fill dielectric. Although gaseous HF hasbeen used to remove thin reactive ion etch (RIE) residues from metallines, it was heretofore believed that the long exposures necessary foroxide dielectric removal were similarly corrosive.

However, as the inventor has found, using gaseous HF, preferably at apartial pressure between 5 and 30 Torr., SiO₂ may be stripped completelyaway from a wiring structure, leaving the metal wires and studs behindunharmed. The gaseous reaction operates through formation of a thinaqueous film.

As a result of that discovery, the inventor further discovered that, inthe microscopic world of these IC wires, other residual forces fromstresses and strains introduced during construction overshadowgravitational forces. By removing the SiO₂ dielectric that normallyencases long IC wiring runs, the freestanding wires are as likely torelax in a lateral or even an upward direction as in a downwarddirection, i.e., they will bow up, down or sideways.

Consequently, in the embodiment a gaseous material, preferably gaseousHF, is used to remove fill material, preferably SiO₂, encasing a wiringstructure. As fill material is removed, sidewall supports are formed tohold the wires in place. Thus, structures formed according to theembodiment method have wires that are supported in all directions.

Referring now to the drawings, and more particularly to FIG. 1 which isa cross-sectional view of wiring, which is preferably in an integratedcircuit with three (3) wiring layers 100, 102, 104. The wiring layers100, 102, 104 are typically a metal such as aluminum or copper. The airdielectric wiring structure, which is formed from the structure of FIG.1 may be limited to a specific area of a chip or may encompass an entirechip.

Although generally referred to herein as metal wiring surrounded by anair dielectric, the present invention may be applied to anymicrostructure that is desired to be freestanding, or entirelyunsupported by underlying material layers. Further, as described herein,the air dielectric structure is shown as being formed in metal wiringlayers 100, 102 and 104. However, an air dielectric structure may extendabove and below layers 100, 102 and 104 and throughout the layers of anintegrated circuit chip with a bottom layer being a polysilicon gatelayer.

Thus, to form an air dielectric structure, first wiring layer 100 isformed above a semiconductor body 106 which may be a silicon substrateor the surface of an insulator layer in, for example, a silicon oninsulator (SOI) wafer. After forming the first wiring layer 100according to any well known process, a thin etch resistant layer 108,preferably silicon nitride or diamond-like crystallized carbon, isformed on the wiring layer 100, at least in an area where a preferredair dielectric structure is to be formed. A first fill material layer110, e.g. an oxide layer, is formed on the thin etch resistant layer108. The second wiring layer 102 is formed on the first insulating layer110. A second fill layer 112 is formed on the second wiring layer 102.The second fill layer 112 is of the same type of fill material as in thefirst 110. The third wiring layer 104 is formed in the second fill layer112 using a damascene process where metal is formed by: a) etchingchannels in layer 112; b) filling the channels with metal; and, then c)polishing the metal off the top of the insulator to leave it in thechannels 114. Alternately, the third wiring layer 104 may be formed onthe second fill layer 112 with fill material formed over the thirdwiring layer 104 to fill between the wires 114 in the third wiring layer104.

Next, in FIG. 2, the structure of FIG. 1 is etched, preferably using ananisotropic reactive ion etch (RIE) with the wiring layers 100, 102 and104 serving as masking layers to remove fill oxide from between wires114 and, thereunder, from fill layers 110 and 112. The anisotropic RIEcontinues until the thin etch resistant layer 108 on the semiconductorbody 106 is exposed or nearly exposed. The RIE leaves walls 120 standingbeneath wires 114 and walls 122 beneath wires 124 on the second metallayer 102. By ending the RIE prior to re-exposing all of thin etchresistant layer 108 in spaces 126, a thin insulating layer 128 remains.

Further, to protect the topmost wiring layer from attack during RIEremoval of the fill oxide, a patterned resist material layer having thesame pattern as the topmost wiring layer may be added to protect theupper wiring layer. Thus, for example an upper aluminum wiring layer maybe protected using the same resist used to define the metal. Thus,immediately after patterning the metal, and before stripping thephotoresist, the oxide is removed in a RIE step.

Next, in FIG. 3, a conformal layer 130 of etch resistant material isformed on the structure of FIG. 2. Preferably, the etch resistantmaterial is silicon nitride. The conformal layer 130 coats the top andside of third wiring level 104, the top and side of the regions ofsecond wiring level 102 that were not masked by third wiring level 104,the top and part of the side of wiring level 100, not masked by 102 or104 and the sides of oxide walls 120, formed during the anisotropic RIEetch.

Horizontal portions of conformal layer 130 are removed using anappropriate anisotropic RIE, leaving sidewalls 132 in FIG. 4 andre-exposing the remaining thin fill layer 128. This re-exposed thin filllayer 128 provides an access to all or nearly all of the remaining fillmaterial. The fill material, which is preferably SiO₂, must be etchableusing gaseous HF, preferably at a partial pressure between 5 and 30torr, with high selectivity to the metal in metal layers 100, 102 and104 and to the sidewall material. Further, it must be removable both byan anisotropic etch, and by an isotropic etch.

An isotropic etch using gaseous HF removes all of the remainingaccessible fill material through the accesses, i.e., all fill materialbetween sidewalls 132 under wiring layers 102 and 104, as well as layer128, leaving behind a honeycomb-like sidewall structure. Thus, virtuallyall of the fill material is removed, leaving behind the wires in layers100, 102 and 104 held in place by the honeycomb-like sidewalls 132. Thesynergistic matrix of interconnected wires and sidewalls so formed isself supporting.

It is important to note that for preferred embodiment wiring, sidewallpedestals between wiring layers need not be aligned throughout theresulting multilayer structure. It is only necessary that each sidewallpedestal rest on or support either another sidewall pedestal or aprevious/subsequent level wire. Furthermore, it is unnecessary that eachsidewall pedestal align with a sidewall pedestal in adjacent layers. Itis only necessary that each sidewall pedestal intersect with anothersidewall pedestal in an adjacent layer. A thin, sub-lithographic layerof dielectric material sidewall may both sufficiently support the wiringand partially coat the wires with dielectric (protecting them fromshorts) without requiring extra masks. As a result a large percentage ofvolume of the final structure is air.

The sidewall pedestals may rest on and be supported by studs of anunderlying wiring level, or by a stiff overlying layer, or somecombination of the two. If the sidewall pedestals do contact anunderlying substrate it is advantageous that they contact a non-planarsubstrate, so that the sidewall pedestals do not seal in the removablefill material, i.e., the SiO₂ pedestals.

The resulting structure is shown in FIG. 4. There is no oxide betweenmetal levels 100, 102 and 104. A thin nitride sidewall 132 is shownbetween metal lines 114. There is a thin nitride sidewall along certainportions of wires in layer 102 (i.e. those not masked by lines 114), andthin vertical nitride plates (coplanar with the sidewalls of metal lines114) join orthogonal vertical nitride plates at wiring layer 102.Although these nitride sidewalls have a higher effective dielectric thanair, they provide needed vertical and lateral rigidity, holding thewires against any lateral motion.

Although the method of the preferred embodiment may be used to form asingle suspended wire, preferably it is used to form multiple levels ofwires in a complex structure. Increased rigidity and improved electricalinsulation also prevents shorts from deformed wiring observed with priorart freestanding wire.

The final etch in the embodiment is an isotropic oxide etch which mustetch oxide with high selectivity to the metal lines and the nitridemasking layers and, further, through channels with a very high aspectratio. The worst case aspect ratios encountered are when directionallyoriented wiring layers align and have the same pitch, e.g. layers 100and 104 in FIG. 4. In such a case, if there are no wires on wiring level102, then the length of a high aspect ratio channel being etched is aslong as the wires run aligned on the two levels. For this case, HF vaporis sufficiently selective and penetrates these high aspect ratiostructures adequately. In general, however, most channels will have muchlower aspect ratios because wiring layers will not have the same wiringpitch and so, will not be in registration with each other.

In an alternate embodiment wiring layer 100 is formed in an undopedoxide. Fill layers 110 and 112 at wiring layers 102 and 104 are dopedsilicon dioxide such as phosphosilica glass (PSG). Since vapor HF etchesPSG with high selectivity to undoped silicon dioxide, in this embodimentetch resistant nitride layer 108 may be eliminated. After stripping PSG,stripping ends at the underlying undoped silicon dioxide, making nitridelayer etch resistant layer 108 unnecessary.

Further, although nitride is the preferred etch resistant material forsidewalls, other suitable materials, such as diamond or diamond-likecarbon which is resistant to etching by vapor HF, and has a lowdielectric constant may be used as well. A suitable sidewall materialmust be an electrical insulator capable of forming along sidewalls,providing structural support, and must be etch resistant to the etchused to remove the fill material when form the air dielectric.

In a second alternate embodiment, the fill material is silicon and thesidewalls are formed by oxidation of the silicon. After siliconoxidation, the remaining underlying silicon may be removed with anisotropic, wet etch using, for example KOH or pyrocatechol. OptionallyChemical Dry Etching (CDE) or another appropriate dry etch may be usedto remove the silicon.

In yet another alternate embodiment, the fill material is removed bydissolution. Using, for example, a damascene process to define metalpatterns directly in a layer of photoresist, the photoresist isanisotropically etched with the metal lines as a mask. Then, a sidewallis deposited. The bottoms of the sidewall are etched using a RIE. Then,the remaining photoresist is removed with a solvent. Alternately, adownstream or other plasma source may be used to remove the residualphotoresist. Further, the fill material may be a water solubleinorganic, such as boron or germanium oxides. Many organics andinorganics can be easily removed by evaporation or thermaldecomposition. Thus, making the fill material of such an organic orinorganic material, it may be removed by thermal decomposition or byevaporation.

Alternately, to minimize exposing the wiring layers 100, 102 and 104 tothe oxide RIE, the sidewall layer may be formed stage by stage as eachwiring layer is formed as represented in FIG. 5. In this embodiment,each wiring layer 140, 142 and 144 masks oxide during RIE down to thenext, lower wiring level. Further, as provided above, photoresist frompatterning the wiring layer 140, 142 and 144 may be left on the wiringpattern to protect it during the RIE. In this alternate embodiment,sidewall pedestals are present along the entire length of each wire ateach level and so, are present in areas that were masked by overlyingwiring patterns in the preferred embodiment. These extra sidewalls formbecause sidewall layers are formed as each wiring layer is formedinstead of deferring sidewall layer formation until the last wiringlayer is formed.

Although each stage is described as a wiring layer, it is contemplatedthat a stage may be two or more layers and that the individual stagesmay each be different multiples of wiring layers. Thus, the first layer140 of layered metal structure is formed of a conductive material suchas aluminum, copper or the like, and patterned by any typical method. Inthis embodiment, the wiring layer 140 or a resist cap (not shown) on thewiring layer 140 acts as a RIE mask. With the wiring layer as mask, fillmaterial is removed from between the wire patterns.

A conformal sidewall layer 148 is deposited on the stripped wiring layer140 and anisotropically etched to remove horizontal portions of thesidewall layer (not shown). A fill material is deposited to fill spacesbetween sidewalls, forming a planar surface. Each subsequent via orwiring layer, e.g., layers 144 and 146, is formed by repeating thesesteps, i.e., pattern wiring, RIE to strip fill down to the next lowerwiring layer, deposit a conformal layer 148′ and 148″, anisotropic RIEto remove horizontal conformal layer portions and deposition ofinterlayer dielectric. After forming all metal levels, the remainingfill is removed using a vapor HF process as described in the aboveembodiment.

In another alternate embodiment shown in FIG. 6, an etch resistantpattern 150 may be formed over the upper metal wiring layer 104 to forma dummy sidewall pattern above wires 152, 154 and 156 of FIG. 7, leavingwire 158 exposed. In this embodiment, the dummy sidewalls provide extrastructural support and, if the fill material is removed using chemicalmechanical polishing (CMP) instead of RIE, pattern 150 provides a ventat the top surface. The resist pattern may be an anisotropicetch-resistant material or a resist pattern transferred in a differentetch resistant material such as silicon nitride. Optionally, the etchresistant pattern 150 may be formed of an etch resistant materialoverlying an additional layer of removable material.

Next, in FIG. 7, after the anisotropic etch, the pattern defined byresist pattern 150 is transferred to the removable dielectric furtherpatterned by wiring layers 100 (wires 160, 162 and 164), 102 and 104. Inthis alternate embodiment, a number of sides are removed that hadremained in the above described embodiment. In particular the sides thatare masked by resist pattern 150 are not formed.

In this embodiment, after the anisotropic etch, a conformal sidewallmaterial is deposited as in the above embodiment. Sidewall material maybe deposited before or after removing the patterned etch resistantmaterial 150. For this embodiment, the conformal sidewall layer may bevented either: by an anisotropic etch removing portions of the conformallayer from horizontal surfaces, as described hereinabove or, by usingCMP to polish portions away from the upper horizontal surfaces.Optionally, if the topmost surface of the region protected by the resistmask 150 may be polished down to expose removable material; then, CMPmay be used to form a vent by removing the top surface until underlyingremovable material is exposed.

FIG. 8A is a top view of the structure of FIG. 7 through A-A, showingthe wiring and the sidewall formed at wiring layer 104. FIG. 8B is a topview of the wiring and the sidewall formed at wiring layer 100 of FIG. 7through B-B, showing sidewall 184 formed as a result of masking fromoverlying metal line 124 in metal layer 102. Sidewalls 184 extend downfrom the wiring layer 102 down to wiring layer 100 and are freestandingat wiring layer 100 and unattached to wiring layer 100. Regions 174 aredefined by resist pattern 150, and attach adjoining wires in layers 100and 104. Sidewall regions 176 are defined by resist pattern 150, and areattached to wiring layer 104, but terminate at the top of wire 124.Sidewall regions at the upper ends (in FIG. 8A) of wires 152-158 aredefined by wiring layer 104 (wires 152-158) and terminate at the top ofwire 124 in wiring layer 102. Sidewall regions at the lower edges ofwires 152-158 and the upper edge of wire 178 are defined by wiring layer104 and extend down to and terminate at the top of wiring layer 100 inregions 180.

An additional sidewall 182 extends upward from the top of wiring layer104 and is present only if the resist pattern 150 is present before theconformal layer is deposited. In this case, sidewalls 174, 176 alsoextend upward from the top of wiring layer 104. Sidewalls 176, 174provide additional lateral support for lines on wiring layer 104.Sidewalls 174 and 184 provide extra lateral support for lines on wiringlayer 100. Sidewall 184 is defined by a metal line 124 on wiring layer102 and is freestanding at layer 100. Sidewall 184, along wiring layer102, as well as wiring layer 102 itself provide lateral support to wire158. Lateral support to line 124 is provided by intersection withsidewalls from lines 152, 154, 156 and 158 in overlying layer 104.

When removing the fill dielectric, the fill dielectric under line 158 onwiring layer 104 is vented from wiring layer 100 between thefreestanding sidewalls 186. Line 152 is vented from regions 190 and 192in layer 100 and region 188 at the upper wiring layer 104. While in thisexample the dielectric under line 178 would not be vented, this canoccur only if there is overlapping wiring of the same pitch andfeatures.

In a variation on this alternate embodiment, as shown in FIG. 9, most ofthe surface is masked, instead of small localized regions and selectedareas 196 are opened through a mask 150′ layer.

Preferably, an anisotropic etch is used to open the openings 196. Theetch resistant layer 150′ may be a composite layer, such as an oxide,nitride, photoresist combination. The structure of FIG. 9 may be coatedwith a conformal layer, or may be filled with a non-removable material.The mask is vented or removed at the top surface by patterned RIE or CMPbefore removing the fill material. Alternatively, if the fill opening196 is coated with a conformal layer, then, anisotropic etching willopen vents in region 196 at 198. If etch resistant layer 150′ is anoxide fill-nitride composite and the vents are plugged after the oxidefill is removed, then the nitride sublayer of etch resistant layer 150′forms a sealed layer, suspended above the entire wiring structure.

Thus, the methods of the present invention define supporting sidewallpedestals after the wiring is defined. The sidewall pedestals are etchedby techniques that leave wiring substantially intact and are formedafter the wiring is formed on or in a removable dielectric. If adirectional etch is used to define the sidewall pedestals, then wiringacts as a mask to underlying removable material, and the sidewallpedestals are mainly to the side of the supported wires.

Further, the preferred removable dielectric is silicon dioxide, widelyused in integrated circuit devices. Thus, the present invention does notrequire extensive process development that might otherwise be requiredwhen using completely new combinations of metal, dielectric, andsidewall. The present invention adds only an oxide RIE step, a sidewalldeposition step, sidewall RIE open, and dielectric removal step to wellknown integrated circuit fabrication processes. With the possibleaddition of an optional step of including a single buried nitride layerto block vapor HF from attacking underlying silicon, these additionalsteps may all occur after the circuit itself is complete. Thus, thepresent invention is based on well known techniques of building wires inSiO₂ that are not available in using completely new structures withdielectrics such as parylene that lack capability of deferred dielectricremoval.

FIG. 10 shows a top view of another alternate embodiment wherein,instead of using an anisotropic etch, an isotropic etch is used to formthe wiring supports. FIG. 11 is a cross-section of the embodiment ofFIG. 10 at A-A. In this embodiment, a small opening 200 (which may beone opening in an array of such openings) is defined through a layer ofisotropically etch resistant material 202. Fill dielectric (SiO₂) isremoved to just below the next underlying layer 102 or deeper, asrepresented by dotted line 204. Non-planar continuous layer 206 is alayer of material or layered material that is impermeable to whateveretchant is used to remove the fill material.

A conformal sidewall layer 199 may be formed before or after removingresist or etch resistant layer 202. Alternatively, the space left byfill material removal may be filled with etch resistant material. Ventsmay be opened in the sidewall layer (not shown) at the bottom of space204 using a RIE to allow fill material removal. Alternatively, CMP orRIE may be used at the upper surface to open vents. Venting may be doneusing isotropic etching, anisotropic etching or combinations thereof. Anisotropic etch is then used to remove any remaining fill material.

A more detailed description follows. After fill, or removable interleveldielectric is removed to dotted line 204 of FIGS. 10 and 11, the cappinglayer 202 is removed and the previously optional sidewall 199 isdeposited as a liner in the hemisphere. FIGS. 10 and 11 show the lineron perimeter 204. Depending on the technique used to form the liner,such as a conformal chemical vapor deposition or a less conformal plasmaenhanced CVD, there will be some liner (not shown) deposited on themetal lines as well. The same removable fill material is redeposited inthe lined trench, it is planarized by CMP and a capping layer of etchresistant material is redeposited and vented by RIE through a patternedmask (which is removed) as before to yield a layer similar to layer 202.The structure is very similar to that described in FIGS. 10 and 11, butthe sidewall 199 is present and vents, not shown, also vent theremovable fill material on the other side of the sidewall material 199.Now, when the removable material is removed, the removable dielectric onboth sides of sidewall 199 is removed. The vents in etch resistant layer202 can then be filled to yield a finished wiring structure with airdielectric.

Optionally, in any of the above embodiments, dummy wires may beselectively included with the circuit wiring to provide additionalwiring support. Further, not all of the fill material may be removed.Some material may be left behind for added strength, while some isremoved for wiring improved capacitance.

FIG. 11 a and FIG. 11 b show an array of vent holes depicted in FIG. 11.If an array of vent holes 200 as in FIG. 11 a are used and pluggedfollowing the isotropic etch, then the result will be a partial airdielectric structure with an array of hemispherical voids, with theuppermost etch front designated by the boundaries 204, surrounded by theremaining removable dielectric 207. This remaining dielectric pillarprovides support walls for the wires, (not shown) which partially orfully span the hemispherical voids. A wire 208 is shown passing thoughthe array of hemispherical voids. It should be understood by thoseskilled in the art that even if the uppermost etch front 204 of thearray of holes 200 overlap (FIG. 11 b), the metal layers underlying thetopmost layer will still be supported by remaining removable dielectric207. Note that the voids are hemispherical if there is little etchingbeyond layer 202 during anisotropic etching of the vent holes 200.However, if an anitsotropic etch extends deeply into the underlyinginterlevel dielectric to the area of the layer 100, the subsequentisotropic etch will produce a void which is more cylindrical.

A wide range of shapes can be etched by a combination of shallow RIE ordeep (see description of FIG. 13 a) multilayer anisotropic RIE etchingof vent holes with a following isotropic etch, to produce hemisphericalor cylindrical etched regions; by combination of deep RIE of largeropenings as in FIG. 9 with a following isotropic etch; and by alteringthe location and density of the array of openings shown in FIGS. 11 aand 11 b. If an oxide with a high etch rate is selected for a particularlayer, then the etch radius of this layer will be greater than for theother layers.

Dielectric structures can be improved by a variation of the methoddescribed above. By way of example, consider the structure of FIG. 5before any removable dielectric is removed, and after any removabledielectric is planarized to be planar with the top of metal level 144.This consists of wiring levels which are supported by sidewalls 148″,148′ and 148 made of a permanent layer which is resistant to a methodused to remove the removable dielectric. An etch resistant layer 202 ispatterned with opening 200 as described in the description of FIGS. 10and 11. An isotropic etch is used to etch a roughly hemispherical regionof the removable dielectric, exposing regions of sidewalls 148″ and148′. An isotropic etch which selectively etches the sidewall thenremoves the sidewall from the hemispherical region to yield thestructure of FIGS. 11 c and 11 d. The same etch which formed thehemisphere is then used to remove the remainder of the removabledielectric to leave a sidewall supported structure outside the originalhemisphere. Improvement in effective dielectric constant is obtainedeven if the sidewall is only partially etched or thinned inside thehemispherical etched region as shown in FIG. 11 d, 148″′.

An alternative method is to form the hemisphere or to etch to completion(complete removal of the removable dielectric) with an etch which alsoattacks the sidewall, but at a reduced rate. The regions of sidewallexposed the longest will be removed or thinned the most.

Moreover, there is a whole class of prior art and yet to be conceivedstructures which combine wiring, air gaps or air dielectric, anddielectric supports. There will exist in each of these structures, asapplied to actual circuitry, at least some regions where the dielectricsupports can be removed (as described above), reduced in size, orreduced in number by etching without causing a detrimental effect uponoverall support of the wiring structure. Such a reduction in dielectricsupport will result in a favorable reduction in the effective dielectricconstant for the wiring of the circuit and corresponding increase incircuit performance and/or reduction in power dissipated within thecircuitry. Intermixing some regions having increased support of wiresamongst other regions having reduced support enables using increasedsupport of wiring in a region where it is needed without increasing theeffective dielectric constant in regions where support is not needed.

In the above-described embodiments, the region to be etched is definedby etching through a small vent to produce a hemispherical region if theetch resistant layer 202 is just opened by RIE; however, the etchedregion will be cylindrical if the RIE proceeds deep into the underlyingdielectric, or of arbitrary shape if the unmasked RIE etched region ofFIG. 7 or 9 is followed by an isotropic etch which removes thedielectric masked by metal lines. After removal of the resist or etchresistant layers 202 or 150, the structure can be (optionally) coatedwith a non-removable sidewall, backfilled with a removable ornon-removable dielectric, a non-removable capping layer added which isvented, and the removable dielectrics removed a second time. Thebackfilled removable dielectric can be the same as or different from theoriginal removable dielectric.

In some respects an etch region which is a section of a hemisphere, asin FIG. 11, or a distorted, stepped section of more than one hemisphere(FIG. 13 b) is an advantageous shape. These shapes are of greater etchedvolume at upper wiring levels. It is precisely these wiring levels whichhave the longest wire runs and the greatest need for reduction in theeffective dielectric constant.

The support dielectric in the etched region can be etched by the sameisotropic or anisotropic etch used to define the etched region, or by aseparate isotropic etch. For instance, in the supported air dielectricwiring structures of FIGS. 1-9, if the original removable dielectric issilicon dioxide and the non-removable, support dielectric is diamondlikecarbon, then the silicon dioxide is removable by a vapor HF etch in adefined region and the diamondlike carbon support dielectric in thatdefined region can be attacked and reduced in thickness or etchedentirely by an oxygen plasma.

Alternatively, in the supported air dielectric wiring structures ofFIGS. 12 and 13, if the original removable dielectric is silicon dioxideand the non-removable, support dielectric is silicon nitride, then thenitride layer and silicon dioxide layer can be removed by RIE in adefined region where it is not masked by overlying metal lines. Backfilling with silicon dioxide, polishing the oxide, capping, venting,then removing the silicon dioxide selectively to nitride with a vapor HFetch will leave a structure in which the metal line masked nitride layerwill provide a reduced support dielectric in the defined region. Thesupport nitride layer is planar, continuous, and not reduced outside thedefined region, wherever the nitride was masked by photoresist duringRIE. In each case the wiring structure is supported by a dielectric withthe wires extending from within the etched region which has reduceddielectric supports to the other side of a non-etched perimeter regionand where the support dielectric was not reduced by the etch.

FIGS. 12 a-12 d show a structure and method of manufacturing analternative embodiment of the present invention having a convex layer(or other non-planar layer) over the wiring layer. Referring to FIG. 12a, any initial wiring layers reside below the surface 300. A layer ofremovable dielectric layer 302, for example, silicon dioxide, isdeposited on surface 300 to form a new surface at level 304. Trenches306 and via trenches 308 are formed in the dielectric layer 302 by, forexample, patterning a layer of photoresist (not shown) then Reactive IonEtching (RIE). The via trenches 308 extends through any dielectriclayers which extend below the surface 300, and down to underlyingstructures which require electrical connection. In particular, if thereare previously formed wiring layers underlying surface 300, the via 308will reach an underlying wiring layer by penetrating a dielectric layeranalogous to layer 316 (of FIG. 13).

FIG. 12 b shows a layer of metal 310, preferably copper, which iselectroplated after removal of photoresist, and after sputter depositionof a continuous metal liner into the trenches 306 and via trenches 308and onto the surface 304. The copper layer 310 and any metal liner isthen polished off surface 304 by CMP to produce metal lines 312 andstuds 314 from the original trenches 306 and vias trenches 308. As seenin FIG. 12 c, if the layer 310 polishes at a lower speed than thedielectric layer 302, then over polishing will produce a metal line 312(one of many metal lines of the wiring layer) and stud 314 with a topconvex shaped surface 322. If the layer 310 polishes at a higher speedthan the dielectric layer 302 then over polishing will produce a concavetop surface of metal lines 312 (shown as dashed line 322 a).

As shown in FIG. 12 c (and FIG. 12 d), the topmost surface of dielectriclayer 302 will lie below the original level 304 of FIG. 12 a afterpolishing. Optionally, the surface of dielectric layer 302 can befurther recessed by RIE, Chemical Downstream Etching, or wet or dry HFetching to level 318 of FIG. 12 c. Referring still to FIG. 12 c, theplanar layer 316 (such as silicon nitride which is not significantlyattacked when dielectric layer 302 is later removed) is deposited andthen a vent 320 is defined by photoresist and etched away. If the wiringlayer is the topmost wiring layer, the dielectric layer 302 is removedthrough the vent 320. After removal of the dielectric layer 302 in theregion shown and in underlying layers, the entire structure is supportedby the planar layer 316, the wiring 312, and the stud 314, the latterwhich connects downward to any wiring and planar layers which may liebeneath surface 300.

FIG. 12 d shows an exploded view of the corner of the wiring which iscircled in FIG. 12 c and represented by “X”. A force vector J (fromresidual stresses in the structure) is shown resolved into componentsparallel, K, and perpendicular, L, to the planar layer 316. The planarlayer 316 follows the convex curvature of the wire 312. This curvatureis formed when over polishing removes the oxide material 302 morerapidly than the metal 312. It is noted that the over polishing lowersthe oxide surface, thus increasing the pressure of the polishing pad onthe corner region 324 of the metal line 312. The additional pressure inthe corner 324 erodes the metal line 312 faster in the corner and leadsto a convex top surface 322. A concave non-planar surface 322 a would beformed if the metal polished faster than the oxide. An optionaladditional etch further lowers the oxide surface to level 318. Clearlythe line so formed is more resistant to detachment from force vector Kthan a line which has a planar attachment to layer 316 and no recess ofthe oxide between metal lines.

The metal lines 312 shown in FIG. 12 c are also less resistant todetachment from force vector L; however, the line is more resistant todetachment from force vector K. It is noted that the metal line 312 ismore resistant than would be a line with a planar attachment to layer316 because the convex surface 322 has a greater attachment area than aflat, planar surface. The vents of FIG. 12 c can be constructed on alayer by layer basis as the wiring is formed; however it is preferableto form the vents after the entire multilayer wiring structure isformed.

Although FIGS. 12 a-12 d show metal lines 312 with a vertical wall whichis perpendicular to the wiring plane and to the plane of layer 316,additional resistance to detachment from force vector L can be obtainedif the wall of the metal lines 312 are sloped, as in depicted by theline “M” in FIG. 12 d. This permits the metal lines 312 to be wider atthe top than at the bottom. A lip 326 of FIG. 12 d may also be used inorder to increase the strength of the structure, since the metal lines312 must now must pass by the lip 326 of FIG. 12 d.

A more complete description of the venting of the structure withpermanent planar overlayers is now provided in FIGS. 13 a and 13 b. Morespecifically, FIG. 13 a shows a structure with several layers of wiring,where the topmost wiring layer includes wires 1158, 1152, 1154, and 1156covered with a relatively thick layer 1150 (e.g., silicon nitride). Thethick layer 1150 is not significantly attacked by the etch used toremove the removable interlayer dielectric (SiO2). The convex surfacesof FIG. 12 c, are not shown for convenience.

The layer 1150 is covered with a photoresist layer 1151 which ispatterned to form an opening 1115. Reactive ion etching of the layer1150 forms a vent opening 1114 which extends down between wires 1158 and1152. Further RIE opens the next layer 1123 (such as silicon nitride ordiamond like carbon, carbon doped dielectric when combined with aremovable dielectric of silicon dioxide) which is chosen to be resistantto attack during the subsequent removal of the interlayer dielectric.The vent opening 1169 does not fully overly the metal line 1124 so RIEcan continue to a lower depth of the structure, terminating at 1168 inFIG. 13 b. If there were additional wiring levels, the reactive ionetching could continue down to open additional vents. Finally, thephotoresist layer 1151 is stripped, and the removable interlayerdielectric associated with metal layers 1104 and 1102 is removed throughthe vent openings 1169. The final etch front 1127 within the removabledielectric is approximately cylindrical in section having apredetermined radius 1128.

In a preferred embodiment, a gaseous HF process is used to remove asilicon dioxide removable interlevel dielectric after all vents areformed (Carbon containing layer/oxygen plasma or even organic polymerremoved by decomposition thermally or by evaporation may be substitutedfor the oxide/vapor HF). Optionally, the interlevel dielectric is notfully removed so that if an array of vent holes is used, there are someregions in the array where remaining interlevel dielectric increasesstrength and rigidity of the resulting partial air dielectric structure.

In an alternative embodiment the vent is formed by an isotropic etch asshown in FIG. 13 b. As previously discussed, the resist layer 1151 ispatterned and RIE is used to open a vent in layer 1150. The vent 1114passes between two metal lines 1158 and 1152 of level 1104 and into theremovable interlevel dielectric of layer 1104. Next, an isotropic etchwhich can etch both the removable interlevel dielectric and the layer1123 is used to form a vent in layer 1123 to form the view shown in FIG.13 b. The resulting etch front 1125 is generally hemispherical (or likea section of a hemsishpere) as the description of FIGS. 10 and 11detail, but circular steps as shown in 1126 are superimposed on thewalls of a somewhat distorted hemisphere if layer 1123 etches at aslower rate than the removable interlevel dielectric. The result is anetch front in the lower removable dielectric (surrounding layer 1102)like a section of hemisphere with a radius 1131 and an etch front in theupper removable dielectric like a section of hemisphere with a radius1130. Stopping at this point and plugging the vent hole 1114 will resultin wiring surrounded by a partial air dielectric with a reducedeffective dielectric constant. However it is preferable to use a secondisotropic etch which selectively removes the removable interleveldielectric with respect to the layer 1123. An array of vents will leaveparallel layers 1150, 1123, and possibly additional layers for eachmetal layer. Each layer will have an array of holes each roughlyconcentric with each adjoining overlying and underlying layer which wasvented by the first isotropic etch. Note in FIG. 13 b that the openingin layer 1150 is roughly concentric with the opening in layer 1123.

Although layer 202 in FIG. 11 or layer 1150 in FIGS. 13 a and 13 b areshown as a single layer, it is contemplated by the present inventionthat these single layers can be composed of a two layers with aremovable dielectric underlying a layer resistant to the etch used toremove the removable dielectric. Thus, the top dielectric bounds theremovable dielectric with the top dielectric either residing on top ofthe upper layer of wiring or residing somewhat above the upper layer ofwiring.

In another aspect of the invention, the air dielectric wiring iscombined with micro-electromechanical (MEMS) devices. This aspect of thepresent invention benefits from a hybrid of two major embodimentsalready described. Sidewall support of the MEMS devices enables use ofsymmetrical vertical structures where there is less susceptibility toresidual stresses than in prior art designs which are substratesupported. The hybrid design also enables easy, economical combinationwith copper wiring with an air dielectric. However, the resistance tostress in the sidewall supported MEMS is obtained whether or not thewiring elsewhere on the integrated circuit has an air dielectric. Thedetailed embodiment showing how MEMS can be combined with transistorcircuit wiring is described below. The transistor circuits can be CMOS,bipolar, a combination or other transistors.

As mentioned previously, a wide range of materials can be used for theremovable material or removable interlevel dielectric, besides silicondioxide. For instance, organic or carbon containing layers like polymersor other carbon containing layers can be used as the removable layerwhen removed by oxygen plasmas or remote oxygen plasmas, or evenorganics which thermally decompose or evaporate can be used. Thepermanent layers or permanent dielectric structures can be composed ofmaterials other than silicon nitride including carbon doped dielectricsor diamond-like carbon if vapor HF etching is used to remove theremovable interlevel dielectric. The permanent layer is resistant to theetch used to remove the removable interlevel dielectric, or otherremovable material but not necessarily completely impervious towardetching. For instance, certain vapor HF etches slowly attack plasmadeposited silicon nitride. It is also interesting to note that althougha removeable interlevel dielectric is specified in the embodiments, adielectric is only preferrable. The embodiments which completely removethe removable layer could in fact use a removable conductor orsemiconductor. The wiring would remain shorted until the removablematerial is completely removed.

FIGS. 14 a-18 c show a cross section of transistor circuit wiring (FIGS.14 a, 15 a, 16 a, 17 a, 18 a), a cross section of the MEMS device (FIGS.14 b, 15 b, 16 b, 17 b, 18 b), and a top down view of the MEMS pattern(FIGS. 15 c, 16 c, 17 c, 18 c). More specifically and referring to FIG.14 a, an underlying wiring layer 510 and 515 is embedded in removableinterlevel dielectric 500. These layers 510 and 515 are capped withlayer 520 which is comprised of a material resistant to the etch to beused later to remove the removable dielectric 500. A layer of resist 530is used to mask layer 520 in the transistor circuit wiring region of thecircuit. RIE is then used to remove capping layer 520 from the MEMSregion of the substrate, and wire 515 of FIG. 15 b (which is exposed bythe RIE) is positioned to serve as a contact for one electrode of a MEMSdevice, such as a switch, capacitor or resonator. Wire 515 could makeelectrical contact with the transistors underlying the MEMS device, orother coplanar wirings (not shown) could make electrical contact tounrelated transistors under the MEMS device.

Transistor gates 531, and 532, were previously formed and underly thecircuit wiring and are part of the circuit. Transistor gates 533 and 534underly the MEMS region. MOS transistors are shown but they could bebipolar or other transistors. The wire 535, preferably copper, is showninterconnecting transistors 531 and 532 as part of a circuit, and wire536 interconnects transistor 533 and 534 as part of a circuit. The layer537 is a layer resistant to the etch used to remove interleveldielectric 500. The layer 537 is horizontal and planar as is layer 520(except where they contact the surface of wire 535, 536, 510, 515 orothers not shown where the contacting surface of the wire may beconcave, convex, or raised relative to the neighboring removabledielectric). Substrate 538 is the silicon in which the transistors areformed. These transistors are understood to be present in FIGS. 15through 18 even though they are not shown. Transistors can underly theMEMS device to be constructed because no direct connection to anunderlying substrate is required.

After the resist 530 is stripped then a multilayer structure isdeposited in the MEMS region of FIG. 15 a. The multilayer of FIG. 15 aincludes metal 540, removable interlayer dielectric 550, metal 560,removable interlayer dielectric 570, and optional RIE stop 580. Resistin the MEMS region 590 of FIG. 15 b is patterned with the pattern 600 ofFIG. 15 c. The entire multilayer stack is etched with an anisotropic RIEprocess which stops on the layer 520 in the wiring layer. The RIE steppatterns both the top and bottom electrode 560 and 540 of the MEMSdevice with the same pattern.

FIGS. 16 a-16 b show the resulting device after removable interleveldielectric 610 is deposited and planarized, and resist layer 620 isformed and patterned. The pattern in the MEMS region is as shown in 640of FIG. 16 c, and is designed to form a trench which will contact thetop electrode 560 of the MEMS device after RIE through opening 630 inresist 620 passes through the removable interlevel dielectric layer 610,optional stop layer 580, and removable interlevel dielectric 570. In thetransistor circuit region, RIE through opening 650 forms a trench whichwill later form a wire which can be used to wire transistors in thetransistor circuit region of the substrate. After RIE, the resist 620 isstripped, and a contact metal liner and copper or other metal isdeposited in the trenches which were formed by RIE through the openings630, 650. Chemical Mechanical Polishing (CMP) removes the metal from thetop surface of the substrate, leaving it in the trenches to form wiringand contacts 700. As previously described, the exposed wire surface ismade non-planar by CMP overpolish of copper or of dielectric 610 or byrecess etching of hte dielectric 610.

FIGS. 17 a-17 b show the structure of the present invention after deeptrenches 670 and 680 are patterned by RIE with resist pattern 660 ofFIG. 17 c. Transistor gates 531, and 532, were previously formed andunderly the circuit wiring and are part of the circuit. Transistor gates533 and 534 underly the MEMS region. MOS transistors are shown but theycould be bipolar or other transistors. Wire 535 is shown interconnectingtransistors 531 and 532 as part of a circuit, and wire 536 interconnectstransistor 533 and 534 as part of a circuit. Layer 537 is a layerresistant to the etch later used to remove interlevel dielectric 500.The layer 537 is horizonal and planar as is layer 520 (except where theycontact the surface of wire 535, 536, 510, 515 or others not shown wherethe contacting surface of the wire may be concave, convex, or raisedrelative to the neighboring removable dielectric). Substrate 538 is thesilicon in which the transistors are formed. These transistors areunderstood to be present in FIGS. 15 through 18, even though not shown.Transistors can underly the MEMS device to be constructed because nodirect connection to an underlying substrate is required.

After trench formation, the deep trenches 670 and 680 are filled with aresistant material, which is resistant to the etch used to remove theremovable dielectric. A layer 690 of the resistant material issimultaneously formed on the wires or contacts 700 (FIGS. 17 a and 17b). Alternatively, the trenches are lined, but not filled with theresistant material. This produces a thin compliant support forresonators where the energy in a vibrating structure must not bedissipated by the support structures. Note that the permanent horizontallayer 690 in the transistor circuit region of FIGS. 17 a and 18 a is ahorizontal planar layer, except where the wiring is made non-planar bychemical mechanical polishing (CMP) or by recessing the surroundingdielectric, 610. The supporting permanent planar layer contacts thenon-planar wire surface in these regions, increasing the area of contactbetween wire and support. Use of sidewall supported electrodes insteadof the prior art substrate supported MEMS elements or electrodes enablesconsiderable process simplification. For example, separate lithographysteps are not required to pattern each electrode and to pattern thedielectric spacer which separates the bottom electrode and substratefrom the top electrode. This reduces to two lithography steps for thesidewall supported MEMS elements of the current invention; onelithography step is required to pattern both electrodes simultaneouslyand one lithography step is required to define sidewall supports.

FIGS. 18 a-18 c show the structure after the resist 715 is patterned toform vents 710 and 720. After resist patterning, RIE is used to etchthrough the layer 690 in both the Transistor circuit and MEMS regions.The pattern in the MEMS region is shown as reference numeral 660 of FIG.18 c. After vent formation, all or part of the removable interleveldielectric is removed from the structure to leave air dielectric in theTransistor circuit region and freestanding electrode plates in the MEMSregion. The electrodes 540 and 560 (shown in FIGS. 15 a and 15 b) arenow freestanding except where supported at the sidewall by sidewallpillars 670 or by contacts. The plate 580 (shown in FIGS. 15 a and 15 b)may also still be present, but does not interfere with operation of theMEMS device. The vent holes can then be plugged by a low pressure plasmadeposited dielectric. Although the term “air dielectric: is used, thewiring and MEMS can be surrounded by a partial vacuum.

FIG. 18 b shows that previously described transistors 533 or 534 ortransistor wiring 536 can even reside directly underneath themicro-electromechanical (MEMS) device because it does not need to have amechanical connection directly underneath the device. The sidewallsupport 670 can connect the edges of each electrode 540 and 560 andupward to planar layer 690 which connects laterally to wire 700, thussupporting the device from above. Although support from above is thepreferred embodiment, it is important to note that a sidewall supportedMEMS device with the sidewall reaching down to a fixed substrate supportis also contemplated by the present invention as is a single moveableelectrode MEMS device with sidewall support.

To this end, consider the previously described embodiment; if layer 500is made of a permanent material instead of a removable material, thenelectrode 540 is fixed by 500 instead of being moveable. There is onlyone moveable electrode 560 with sidewall support down to the underlyingfixed substrate support. A MEMS device with a single moveable electrodewhich is supported by a sidewall support likewise has simplifiedconstruction and reduced interference, reduced energy dissipation, andreduced electrode bowing with a sidewall support, especially if thesidewall is made very thin. If the sidewall is compliant, some stresscan be relieved by motion of the sidewall support instead of byelectrode bowing.

The MEMS device of FIGS. 15-18 have two electrodes 540, 560 which areplaced opposing each other separated by a small gap 730 with a dimensiondetermined by the thickness of the removable material 550 (which islater removed to make both electrodes moveable). In operation, therelative distance of the two electrodes can change as there is movementin response to a voltage difference applied between them. Although theabove embodiments describe metal electrodes, the electrodes could alsobe a dielectric with conductive or metal areas embedded in thedielectric. It is important to note that MEMS with two moveableelectrodes is a novel structure, especially when both electrodes are ofsimilar construction and therefore have similar stresses (and even whenconstructed without sidewall support). However, it is easier to havesimilar electrode shapes, supports and stresses with sidewall supportbecause there is no need to have a patterned permanent dielectricsupport (which makes identical smooth electrode surfaces difficult)between the opposing electrodes, or to have electrodes supported bydistant contacts to an underlying substrate.

FIGS. 18 a-18 c show how stresses within the electrodes relax. Assumethe electrode 540 and the electrode 560 both are built with(compressive) stress shown by arrow 740. When the removable material isremoved to enable movement of the electrodes, they will respond bybuckling downward in the direction shown by arrow 750. If the electrodesare similar, with similar stresses, and similar support, the bucklingwill be matched in each electrode, with little change in relativeelectrode spacing.

In the embodiment just described, a number of processes can be carriedout simultaneously in the MEMS and the transistor circuit regions. Forinstance, the wiring, 700, in the circuit region and the wiring used tomake electrical contact to the MEMS device, 700, are formedsimultaneously, the supports in the MEM region, 670 and 690, and for thewiring in the transistor region, 680 and 690, are formed simultaneously.The dielectric, 500 and 610, in the transistor region and in the MEMSregion are simultaneously removed.

Thus, as seen in FIGS. 14 a-18 c, the wiring is supported predominantlyby the planar layers which are parallel to the wafer surface 690, andthe MEMS device and relative electrode spacing is supported by anddetermined by sidewall pillars 670. It would be impossible to supportthe MEMS device and maintain the relative electrode spacing with planarlayers such as layer 690. Thus, the hybrid support with planar layers inthe Transistor circuit wiring and sidewall support in the MEMS region isideal.

It is important to note that since both electrodes of the MEMS deviceare freestanding, and since both electrodes have experienced similarprocess treatments, the stresses within each electrode is similar. Also,since both electrodes are supported in a similar fashion, the movementsand deformations of the final structure which enable relief of those“stresses of construction” are similar. This enables a narrower gapbetween the electrodes. This is in contrast to a device with oneelectrode fixed on a substrate and one movable electrode. In this casestresses of construction will be released by motion of only oneelectrode, and resulting bowing or motion will alter the gap between theelectrodes and perhaps even cause shorting of electrodes. Also, bothelectrodes of the present invention are able to move in response to anapplied voltage, therefore switches or capacitors or resonatorsconstructed with two movable electrodes will have a greater response toa given applied voltage than with one electrode fixed and only onemoveable.

The resulting structure of the present invention is also resistant toundesireable relative motion of the two MEMS electrodes caused by suddenacceleration of the device (such as caused by dropping). Since bothelectrode plates are movable and are of similar construction, mostmotion will be experienced by both plates, leading to little relativemotion. This again is in contrast to prior art construction where oneplate is fixed by a substrate. Neither MEMS electrode nor sidewallsupports must make contact with the underlying substrate enablingtransistors to underly the MEMS device and unrelated wiring to coexistin the same region. The MEMS electrodes are suspended above the siliconsubstrate.

In view of the above description, those of ordinary skill in the artshould now recognize, in addition to the above, the following advantagesof the present invention:

-   -   1. Planar support in wiring, in combination with sidewall        support, and sidewall support in MEMS;    -   2. A process sequence having common multiple steps thus lowering        costs. These common process sequences include air gap formation,        contacts, wires, formation of support materials, etc;    -   3. The present invention can use a dissimilar MEMS material;    -   4. The present invention is useful for AC/DC switch and voltage        operated capacitor;    -   5. The formation of the MEMS of the present invention have a        structure with less sensitivity to stresses;    -   6. The formation of MEMS of the present invention have a        structure less susceptible to acceleration;    -   7. The formation of MEMS of the present invention have high        electrical conductivity contact and wiring (Cu elements);    -   8. The formation of MEMS of the present invention have having        improved drive voltage/gap trade-off. (switch, capacitor and        resonator);    -   8. There is a simplified construction due to the suspension of        MEMS devices without substrate contact; and    -   9. The formation of MEMS having unrelated wiring underneath.    -   10. The formation of MEMS having transistors positioned        underneath the MEMS.

As described herein, the embodiments include wiring structures fromwhich SiO₂ has been removed using gaseous HF. Prior art wiringstructures may be improved using an SiO₂ fill which is subsequentlyremoved using gaseous HF. For example support type wiring structures maybe formed much more simply by forming the HF resistant supports in SiO₂and then removing the SiO₂ using gaseous HF.

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced

1-18. (canceled)
 19. A method of forming a wiring structure comprisingthe steps of: forming a removable dielectric structure with wiringcontained within the removable dielectric structure, the wiringincluding wire levels; and etching multiple regions of the removabledielectric structure to form air gaps, wherein the wiring extends fromwithin the etched region to an adjacent non-etched perimeter region. 20.The method of claim 19, comprising refilling the multiple etched regionswith a removable dielectric layer.
 21. The method of claim 20, furthercomprising capping the etched multiple regions with a capping layerafter the refilling step.
 22. The method of claim 21, furthercomprising: forming a vent hole in the capping layer; removing theremovable dielectric layer; and plugging the vent hole.
 23. The methodof claim 19, further comprising the steps of: forming a permanentstructure in contact with and supporting the wiring while forming theremovable dielectric structure; and etching the permanent structureexposed within the multiple etched regions, wherein the step of etchingthe permanent structure first includes etching the multiple etchedregions, and the wiring and the permanent structure are contained withinthe removable dielectric structure.
 24. The method of claim 23, wherein:the permanent structure is a horizontal layer in contact with the wiringcontained within the removable dielectric structure; and the horizontallayer is at least two horizontal layers; the etching step is anisotropic etch which etches the removable structure and further etchesthrough at least one of the horizontal layers thereby forming themultiple etched regions, the multiple etched regions are sections ofmultiple hemispheres.
 25. The method of claim 19, further comprising:refilling the multiple etched regions with a removable dielectric layer;forming a permanent layer on a surface of the non-etched perimeterregion prior to the refilling step; and capping the etched multipleregions after the refilling step, wherein the multiple etched regionsare formed by isotropic etching through a capping layer formed by thecapping step which is substantially removed.
 26. The method of claim 25,further comprising venting the permanent structure to provide access toremovable material of the removable dielectric structure residing withinthe non-etched perimeter region.
 27. The method of claim 19, furthercomprising forming a capping layer prior to the etching of the multipleregions.
 28. The method of claim 27, wherein the multiple etched regionsare defined by forming vents in the capping layer and isotropicallyetching the underlying removable dielectric structure.
 29. The method ofclaim 19, further comprising: forming a permanent structure for at leastone of the wire levels of the wiring by etching a wire trench and a viatrench in the removable dielectric structure, wherein the permanentstructure includes: depositing a metal liner in the wire trench;electroplating copper on the metal liner; and polishing the metal linerand the copper from a surface of the removable dielectric structure, anddepositing a layer of dielectric on the metal liner which is to form apermanent layer.
 30. A method of forming a wiring structure comprisingthe steps of: forming at least a transistor on a substrate in a firstregion; forming a multilayered stack wiring level containing at leastone conductor and removable material layer in a second region adjacentto the first region; patterning the at least one conductor to form anelectrode of a micro-electromechanical (MEMS) device; simultaneouslyforming removable interlevel dielectric overlying the transistors of thefirst region and surrounding the multilayer stack of the second regionwhich connect to the transistors; forming wires which interconnect withthe MEMS device; forming air dielectric by removing the removableinterlevel dielectric simultaneously overlying the transistors in thefirst region and the second region; and removing the removable materialto form a moveable electrode.
 31. The method of claim 30, furthercomprising: simultaneously forming a permanent dielectric within thesecond region overlying the transistors of the first region, wherein thepermanent dielectric being resistant to attack by a method used toremove the removable dielectric, the permanent dielectric interconnectsand supports the wiring, and the permanent dielectric connects to andsupports the at least the conductor of the multilayer stack wiringlevel.
 32. The method of claim 30, wherein the wiring is formed by:forming trenches in the removable dielectric; depositing a conductivelayer on walls of the trenches; electroplating copper on the surface ofthe conductive layer; and polishing the copper from a top surface of theremovable dielectric to leave a copper line within the trenches.
 33. Themethod of claim 32, wherein: the multilayered stack wiring layer is atleast two multilayered stack wiring layer, one of the at least twomultilayered stack wiring layers has a top conductor layer, the methodincluding the further steps of: forming trenches in the removabledielectric, wherein at least a first set of trenches in the secondregion being formed over an edge of the multilayered stack wiring layer;depositing a contact in at least a second set of trenches contacting atop conductor layer of one of the multilayered stack wiring layers; andforming vents in the first region and the second region.
 34. A method offorming a micro electromechanical structure with two moveable elementscomprising the steps of: forming a first layer which includes a firstarea of at least one material which will become a first moveableelement; depositing a removable dielectric to form a first removablespacer; forming a second layer which includes a second area of at leastone material which will become a second moveable element onto theremovable spacer, the second area overlying the first area; forming andpatterning a material which overlies the first area and the second area,wherein the patterned material is a mask for etching; etching a firstedge of the first area and a second edge of the second area where thesecond edge directly overlies said first edge; depositing a resistantmaterial which is resistant to a method used to remove the removablespacer to form a layer which connects the first edge to the second edge;and removing the removable dielectric.
 35. The method of claim 34,further comprising depositing a layer of removable dielectric prior tothe forming and patterning step in order to form a second removablespacer overlying the second area.
 36. The method of claim 35, furthercomprising forming a supporting region which supports the microelectromechanical structure, the supporting region being resistant toremoval during removal of the removable material, prior to thedepositing of the of the resistant material, wherein the resistantmaterial connects the first edge to the second edge to the supportingregion.